1. Field of the Invention
The present invention relates to an electronic component including a substrate that has been singulated from a mother substrate. More specifically, the present invention relates to an electronic component including an electronic component element arranged on a substrate so that a functional circuit portion of the electronic component element is spaced apart from an upper surface of the substrate.
2. Description of the Related Art
In the related art, an electronic component manufacturing method is widely known and including placing a plurality of electronic component elements on a mother substrate, and then cutting the mother substrate. For example, the following manufacturing method is described in Japanese Unexamined Patent Application Publication No. 2001-44324 mentioned below.
According to the manufacturing method described in Japanese Unexamined Patent Application Publication No. 2001-44324, first, a mother substrate having a plurality of semiconductor chip placement areas provided on its upper surface is prepared. On the upper surface of this mother substrate, a number of electrodes are formed in individual semiconductor element chip placement areas. In addition, on the upper surface of the mother substrate, a cutting line checking pattern is formed on a cutting line along which the mother substrate is cut into individual electronic component units. This cutting line checking pattern is formed in a second area that is located outside a first area where a plurality of semiconductor element chips are placed. That is, the cutting line checking pattern is formed at a position where the cutting line along which the mother substrate is cut extends within the second area.
According to the manufacturing method mentioned above, after placing the plurality of semiconductor element chips, a sealing resin layer is formed so as to cover the first area. Thereafter, the mother substrate is cut along the cutting line passing through the cutting line checking pattern that is exposed in the second area.
As the miniaturization of electronic component chips advances, the dimension between the electrodes of electronic component chips becomes smaller, and so does the dimension between the corresponding electrodes on a mother substrate which are joined to the electrodes of the electronic component chips. Consequently, positioning of electronic component element chips becomes difficult. In particular, when joining to electrodes on the substrate by using bumps, there is a possibility that misalignment of the joints between the bumps and the electrodes may lead to a decrease in joint strength.
According to the manufacturing method described in Japanese Unexamined Patent Application Publication No. 2001-44324, there is a possibility of erroneous mounting occurring during placement of semiconductor element chips executed prior to cutting. Although the cutting line checking pattern mentioned above is used for the positioning that is executed when finally cutting a composite substrate, it is also possible to mount semiconductor element chips by using the cutting line checking pattern as a reference. However, as electronic component chips such as semiconductor element chips are miniaturized as mentioned above, it is difficult to position and mount electronic component chips with high accuracy solely by using the cutting line checking pattern provided in the second area as a reference.
FIGS. 15 and 16 are schematic plan views each illustrating an example of such erroneous mounting. In FIG. 15, areas on a mother substrate 1001 which are enclosed by cutting lines indicated by broken lines A1 and A2 represent individual electronic-component-element placement areas. As indicated by a solid line in FIG. 15, there is a possibility that an electronic component element chip 1002 may be erroneously mounted so as to straddle adjacent electronic-component-element-chip placement areas.
In some cases, individual electronic component element chips are placed after dividing the mother substrate into individual substrates. In such cases as well, as illustrated in FIG. 16, when a plurality of substrates 1001A are arranged in a grid form owing to the division of the mother substrate, there is also a possibility that the electronic component element chip 1002 may be mounted so as to straddle adjacent substrates 1001A.